Thin film transistor liquid crystal display panel driving device and method thereof

ABSTRACT

A thin film transistor (TFT) liquid crystal display panel driving device and a method thereof are provided. The TFT liquid crystal display panel driving device is characterized by including a modulation signal generator for providing at least one modulation signal to at least one output buffer of a source driver of the TFT liquid crystal display panel. The output buffer(s) has chopper function. Each output buffer changes the offset voltages of the pixels of a same frame under the control of different modulation signals, thus eliminating the effect of the offset voltages of the output buffer(s) on the display quality.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of Taiwan applicationserial no. 95113133, filed on Apr. 13, 2006. All disclosure of theTaiwan application is incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of Invention

The present invention relates to a display panel driving device and amethod thereof, and more particularly, to a TFT liquid crystal displaypanel driving device and a method thereof.

2. Description of Related Art

At present, the mainstream TFT liquid crystal display panel adopts anoperational amplifier to drive the pixel units on a display at differentvoltages, so as to display different frames on the display. Therefore,the display quality of the display and the features of the operationalamplifier are highly correlative. The main variable of the operationalamplifier affecting the frame quality is offset voltage generated due tochanges in the process. Conventionally, two conventional methods aremainly used to eliminate the offset voltage: one is auto zeroing,wherein a capacitor is required to store the offset voltage, resultingin the need of extra control signals and increase of the circuit area;and the other is using a chopper to compensate the offset voltage.

FIG. 1A is a block diagram of a driving device of a conventional TFTliquid crystal display panel adopting a chopper. Display data 1˜n areinput into operational amplifiers 12_1˜12_n with chopper functionthrough digital-to-analog converters 11_1˜11_n. A control signalcontrols the operational amplifiers 12_1˜12_n to modulate the offsetvoltages. The operational amplifiers 12_1˜12_n output voltages tochannels 1˜n. FIG. 1B is a voltage-to-time diagram of the polarity (POL)signal and control signal of FIG. 1A, wherein the longitudinal axis ofFIG. 1B represents voltage and the horizontal axis represents time. Inthe most common dot inversion driving architecture at present, the POLsignal controls the output polarity of the source driver and isconverted at every one frame, wherein frames F11, F12, F13, F14 aredisplayed at the time periods 0˜T11, T11˜T12, T12˜T13, T13˜T14. Thecontrol signal is Logic 1 at frames F11 and F12, and Logic 0 at framesF13 and F14. FIG. 1C is a voltage-to-time diagram of an ideal outputwaveform 102 and an actual output waveform 101 in FIG. 1A, wherein thelongitudinal axis of FIG. 1C represents voltage and the horizontal axisrepresents time. When the frame F11 is displayed, the voltage of theideal output waveform 102 is VP1, and the voltage of the actual outputwaveform 101 is V1, thus generating an offset voltage of V1−VP1=ΔV. Whenthe frame F12 is displayed, the voltage of the ideal output waveform 102is VN1, and the voltage of the actual output waveform 101 is V2, thusgenerating an offset voltage of V2−VN1=ΔV. When the frame F13 isdisplayed, the offset voltage is V3−VP1=−ΔV. When the frame F14 isdisplayed, the offset voltage is V4−VN1=−ΔV. FIG. 1D is an offsetvoltage distribution diagram of the frames F11˜F14. The offset voltagesof the pixels in the frames F11 and F12 are all ΔV, while those offrames F13 and F14 are all −ΔV. As the human eye can be considered to bea low-pass filter, after the control signal controls the operationalamplifier with chopper function for a short period of time, the humaneye can compensate the offset voltage, and thus the offset voltage is 0to the human eye.

Though the method solves the offset voltage problem of the operationalamplifier, taking 60 frames per second as an example, for each pixel onthe panel, there are 30 positive polarity voltages and 30 negativepolarity voltages on the pixel. To compensate the offset voltages, the30 positive polarity voltages and 30 negative polarity voltages arerespectively further divided into 15 positive offset voltages and 15negative offset voltages. The frequency of a chopper is a quarter thatof a frame, and under such a low time frequency, the human eye caneasily sense the changes in brightness in the whole area, thus causingthe frame flickering phenomenon. Therefore, as the aforementionedconventional art uses time modulation to control the chopper, the framequality is greatly degraded.

SUMMARY OF THE INVENTION

An objective of the present invention is to provide a liquid crystaldisplay panel source driving device for providing different modulationsignals to output buffers controlling two portions of pixels in the sameframe, so as to eliminate the adverse effect of the offset voltages,prevent the frame flickering phenomenon, reduce the area of theintegrated circuit and improve the display quality.

Another objective of the present invention is to provide a TFT liquidcrystal display panel driving method for providing different modulationsignals to output buffers controlling two portions of pixels in a frame,so as to eliminate the adverse effect of the offset voltages, reduce thearea of the integrated circuit, prevent the frame flickering phenomenonand improve the display quality.

Another objective of the present invention is to provide a TFT liquidcrystal display panel driving device for providing different modulationsignals to output buffers at the odd and even output ends of the sourcedriver, so as to eliminate the adverse effect of the offset voltages,save circuit elements, prevent the frame flickering phenomenon andimprove the display quality.

Another objective of the present invention is to provide a TFT liquidcrystal display panel driving method for providing different modulationsignals to output buffers at the odd and even output ends of the sourcedriver, wherein the modulation signals are changed according to the oddand even scan lines of the output buffers in the frame, so as toeliminate the adverse effect of the offset voltages, save the circuitelements, prevent the frame flickering phenomenon and improve thedisplay quality.

Another objective of the present invention is to provide a TFT liquidcrystal display panel driving device, wherein the modulation signals arechanged according to the odd and even scan lines in the frame, so as toeliminate the adverse effect of the offset voltages caused by processdifferences, reduce the area of the integrated circuit, prevent theframe flickering phenomenon and improve the display quality.

Another objective of the present invention is to provide a TFT liquidcrystal display panel driving method, wherein the modulation signals arechanged according to the odd and even scan lines in the frame, so as toeliminate the adverse effect of the offset voltages caused by processdifferences, prevent the frame flickering phenomenon, reduce the area ofthe integrated circuit and improve the display quality.

Another objective of the present invention is to provide a TFT liquidcrystal display panel driving device for providing different modulationsignals to output buffers at the odd and even output ends of the sourcedriver, wherein the modulation signals are changed according to the oddand even scan lines in the frame, so as to improve the display quality,eliminate the adverse effect of the offset voltages caused by processdifferences, reduce the circuit area and prevent the frame flickeringphenomenon.

Another objective of the present invention is to provide a TFT liquidcrystal display panel driving method for providing different modulationsignals to output buffers at the odd and even output ends of the sourcedriver, wherein the modulation signals are changed according to the oddand even scan lines in the frame, so as to improve the display quality,eliminate the adverse effect of the offset voltages caused by processdifferences and prevent the frame flickering phenomenon.

To achieve the above or other objectives, the present invention providesa liquid crystal display panel source driving device comprising at leastone output buffer and a modulation signal generator, wherein the outputbuffer(s) has chopper function and the modulation signal generatorprovides at least one modulation signal to the output buffer(s). Whenthe pixel data of a first portion of a frame is output, the modulationsignals received by the output buffers for outputting the pixel data ofthe first portion are all in a first state. When the pixel data of asecond portion of the frame is output, the modulation signals receivedby the output buffers for outputting the pixel data of the secondportion are all in a second state. Moreover, the numbers of the pixelsin the first portion and the second portion are approximately the same.

From another point of view, the present invention further provides a TFTliquid crystal display panel driving method. When the pixel data of thefirst portion of a frame is output, at least one modulation signal inthe first state is provided to at least one output buffer for outputtingthe pixel data of the first portion in the source driver of the TFTliquid crystal display panel, wherein the output buffer has chopperfunction. When the pixel data of the second portion of the frame isoutput, the modulation signal in the second state is provided to theoutput buffer for outputting the pixel data of the second portion.Moreover, the numbers of the pixels in the first portion and the secondportion are approximately the same.

From another point of view, the present invention further provides a TFTliquid crystal display panel driving device. The device is characterizedby comprising a modulation signal generator for providing the firstmodulation signal to at least one output buffer at the odd output endsin the source driver of the TFT liquid crystal display panel, andproviding the second modulation signal to at least one output buffer atthe even output ends in the source driver, wherein the output buffersall have chopper function. When the first and the second frames areoutput, the first modulation signal is in the first state and the secondmodulation signal is in the second state. When the third and the fourthframes are output, the first modulation signal is in the second stateand the second modulation signal is in the first state.

From another point of view, the present invention further provides a TFTliquid crystal display panel driving method, which comprises providingthe first modulation signal to at least one output buffer at the oddoutput ends in the source driver of the TFT liquid crystal displaypanel, and providing the second modulation signal to at least one outputbuffer at the even output ends in the source driver, wherein the outputbuffers all have chopper function. When the first and the second framesare output, the first modulation signal is in the first state and thesecond modulation signal is in the second state. When the third and thefourth frames are output, the first modulation signal is in the secondstate and the second modulation signal is in the first state.

From another point of view, the present invention further provides a TFTliquid crystal display panel driving device. The device is characterizedby comprising a modulation signal generator for providing modulationsignals to at least one output buffer in the source driver of the TFTliquid crystal display panel, wherein the output buffers all havechopper function. When the odd scan lines of the first and the secondframes and the even scan lines of the third and the fourth frames areoutput, the modulation signals are in the first state. When the evenscan lines of the first and the second frames and the odd scan lines ofthe third and the fourth frames are output, the modulation signals arein the second state.

From another point of view, the present invention further provides a TFTliquid crystal display panel driving method. The method is characterizedby providing a modulation signal to at least one output buffer in thesource driver of the TFT liquid crystal display panel, wherein theoutput buffers all have chopper function. When the odd scan lines of thefirst and the second frames and the even scan lines of the third and thefourth frames are output, the modulation signal is in the first state.When the even scan lines of the first and the second frames and the oddscan lines of the third and the fourth frames are output, the modulationsignal is in the second state.

From another point of view, the present invention further provides a TFTliquid crystal display panel driving device. The device is characterizedby comprising a modulation signal generator for providing the firstmodulation signal to at least one output buffer at the odd output end inthe source driver of the TFT liquid crystal display panel and providingthe second modulation signal to at least one output buffer at the evenoutput end in the source driver, wherein the output buffers all havechopper function. When the odd scan lines of the first and the secondframes and the even scan lines of the third and the fourth frames areoutput, the first modulation signal is in the first state and the secondmodulation signal is in the second state. When the even scan lines ofthe first and the second frames and the odd scan lines of the third andthe fourth frames are output, the first modulation signal is in thesecond state and the second modulation signal is in the first state.

From another point of view, the present invention further provides a TFTliquid crystal display panel driving method. The method comprisesproviding the first modulation signal to at least one output buffer atthe odd output end in the source driver of the TFT liquid crystaldisplay panel, and providing the second modulation signal to at leastone output buffer at the even output end in the source driver, whereinthe output buffers all have chopper function. When the odd scan lines ofthe first and the second frames and the even scan lines of the third andthe fourth frames are output, the first modulation signal is in thefirst state and the second modulation signal is in the second state.When the even scan lines of the first and the second frames and the oddscan lines of the third and the fourth frames are output, the firstmodulation signal is in the second state and the second modulationsignal is in the first state.

In the present invention, different modulation signals are applied tooutput buffers corresponding to individual pixels of a frame and ahigh-frequency space modulation is used to substitute the low-frequencytime modulation, so as to eliminate the adverse effect of the offsetvoltages caused by process differences after the automatic compensationof the human eye, and also prevent the frame flickering phenomenon inthe conventional art and improve the display quality due to thesignificant increase in the modulation frequency. Moreover, the presentinvention does not require a capacitor to store the offset voltages,thus reducing the area of the integrated circuit.

In order to make the aforementioned and other objects, features andadvantages of the present invention comprehensible, preferredembodiments accompanied with figures are described in detail below.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a block diagram of the driving device of the conventional TFTliquid crystal display panel with a chopper.

FIG. 1B is a voltage-to-time diagram of the POL signal and the controlsignal in FIG. 1A.

FIG. 1C is a voltage-to-time diagram of the ideal output waveform 102and the actual output waveform 101 in FIG. 1A.

FIG. 1D is an offset voltage distribution diagram of the frames F11˜F14.

FIG. 2A is a block diagram of the driving device of the TFT LCDaccording to an embodiment of the present invention.

FIG. 2B is a block diagram of the driving device of the TFT LCDaccording to another embodiment of the present invention.

FIG. 2C is a circuit block diagram of the source driver 23_1.

FIG. 2D is a flow chart diagram of the operation of the modulationsignals CNTRL1 and CNTRL2.

FIG. 2E is a circuit diagram of the output buffer 233_1.

FIG. 2F is a circuit diagram of another embodiment of the output buffer.

FIG. 3A is a voltage-to-time diagram of the POL signal, modulationsignal CNTRL1, modulation signal CNTRL2 according to an embodiment ofthe present invention.

FIG. 3B is a voltage-to-time diagram of the ideal output waveform 301and the actual output waveform 302 of the output buffer 233_1.

FIG. 3C is a voltage-to-time diagram of the ideal output waveform 303and the actual output waveform 304 of the output buffer 233_2.

FIG. 3D is an offset voltage distribution diagram of the frames F31˜F34according to an embodiment of the present invention.

FIG. 4 is an offset voltage distribution diagram of the frames F41˜F44according to another embodiment of the present invention.

FIG. 5 is an offset voltage distribution diagram of the frames F51˜F54according to another embodiment of the present invention.

FIG. 6 is an offset voltage distribution diagram of the frames F61˜F64according to another embodiment of the present invention.

DESCRIPTION OF EMBODIMENTS

FIG. 2A is a block diagram of the driving device of a TFT LCD accordingto an embodiment of the present invention. A vertical synchronizationsignal functioning as an activating signal for eliminating the offsetvoltages is input into source drivers 23_1, 23_2 . . . of a TFT liquidcrystal display panel driving device 230. The source drivers 23_1, 23_2. . . drive the liquid crystal display panel together with gate drivers22_1 . . . . FIG. 2B is a block diagram of the driving device of the TFTLCD according to another embodiment of the present invention. FIG. 2Band FIG. 2A are different in that the first output signal of the gatedriver 22_1 is used as an activating signal.

Each source driver of the present embodiment has the same structure, thesource driver 23_1 is taken as an example, and FIG. 2C is a circuitblock diagram of the source driver 23_1. Image data is input into aprocessing unit 231 for pretreatment, and the display data 1˜n areoutput to digital-to-analog converters 232_1˜232_n and then output tothe channels 1˜n through the output buffers 233_1˜233_n. A modulationsignal generator 234 generates modulation signals CNTRL1 and CNTRL2, andchanges the logic states of the modulation signals CNTRL1, CNTRL2according to the activating signal. Here, the activating signal can be avertical synchronization signal or the first output signal of the gatedriver 22_1, for representing the starting time point of each frame. Themodulation signal CNTRL1 is input into odd output buffers 233_1, 233_3 .. . , and the modulation signal CNTRL2 is input into even output buffers233_2, 233_4 . . . . The output buffers 233_1˜233_n all have chopperfunction, and the modulation signals CNTRL1, CNTRL2 are used toeliminate the adverse effect of the offset voltages of the output buffer233 on the frame quality. In the embodiment, the source driver is asource driving device, which utilizes the modulation signal generator234 to control the output buffers 233_1˜233_n, so as to eliminate theoffset voltages and thereby drive the device of the liquid crystaldisplay panel.

FIG. 2D is a flow chart diagram of the operation of modulation signalsCNTRL1 and CNTRL2. Initially, the preset modulation signals CNTRL1,CNTRL2 are loaded in Step S201. Then, in Step S203, the modulationsignals CNTRL1, CNTRL2 are used and in Step S205, whether an activatingsignal is received is determined. Here, the activating signal can be aPOL signal, a vertical synchronization signal or the first output signalof the gate driver 22_1, or another signal synchronous with the startingtime of each frame. If the activating signal is not received, theoperation goes back to Step S203 of using the current modulation signalsCNTRL1 and CNTRL2. If the activating signal is received, the logicstates of the modulation signals CNTRL1 and CNTRL2 are changed in StepS207.

The output buffers in the present embodiment have various structures,the output buffer 233_1 is taken as an example, and FIG. 2E is a circuitdiagram of the output buffer 233_1. The output buffer 233_1 receives themodulation signal CNTRL1 to output two different offset voltages. Forease of representation, a signal φ2 is used to represent the modulationsignal CNTRL1 and a signal φ1 is used to represent the invertedmodulation signal /CNTRL1 in FIG. 2E. The signal φ2 controls switchesSW2, SW4, SW6, SW8, and the signal φ1 controls switches SW1, SW3, SW5,SW7. A positive input end P1 and a negative input end N1 of the outputbuffer 233_1 are respectively connected to a control end of a P-type MOStransistor T1 and a control end of a P-type transistor T2 throughswitches SW1, SW2 and switches SW3, SW4, so as to input the voltages atthe input ends P1, N1 in time sequence into a differential transistorpair formed by transistors T1 and T2. One end of a current source i1 iscoupled to a voltage VCC and the other end is coupled to the transistorsT1, T2, for providing a driving current to the transistors T1 and T2.Besides, the other ends of the transistors T1 and T2 are respectivelycoupled to an N-type MOS transistor T3 and an N-type MOS transistor T4,for outputting the driving current to a control end of an N-type MOStransistor T5 under the control of switches SW5, SW6, SW7 and SW8. Acurrent source i2 provides a driving current to the transistor T5 andthe transistor T5 outputs output voltages of two offset voltages from anoutput end Vout in time sequence.

FIG. 2F is a circuit diagram of another embodiment of the output buffer233_2. In FIG. 2F, the output buffer 233_2 receives the modulationsignal CNTRL1 to output two different offset voltages. The differencebetween FIG. 2F and FIG. 2E is that, in FIG. 2E, the transistors T1, T2of the differential transistor pair coupled to the input ends P1, N1 areboth P-type MOS transistors and the other transistors T3, T4, T5 areN-type MOS transistors; while in FIG. 2F, the transistors T6, T7 of thedifferential transistor pair coupled to the input ends P2, N2 are bothN-type MOS transistors and the other transistors T8, T9, T10 are P-typeMOS transistors. The positive input end P2 and the negative input end N2of the output buffer 233_2 are respectively connected to a control endof the transistor T6 and a control end of the transistor T7 throughswitches SW9, SW10 and switches SW11, SW12. One end of a current sourcei3 is coupled to a voltage GND while the other end is coupled to thetransistors T6 and T7, for providing a driving current to thetransistors T6 and T7. Besides, the other ends of the transistors T6 andT7 are respectively coupled to transistors T8 and T9, for outputting thedriving current to a control end of the transistor T10 under the controlof switches SW13, SW14, SW15 and SW16. A current source i4 provides adriving current to the transistor T10 and the transistor T10 outputsoutput voltages of two offset voltages from an output end Vout2 in timesequence. FIGS. 2E and 2F are only two examples of the output buffer,and the output buffers can be optionally designed as output buffers inother forms with chopper function.

FIG. 3A is a timing diagram of the POL signal, modulation signal CNTRL1,and modulation signal CNTRL2 according to an embodiment of the presentinvention. Frames F31, F32, F33, F34 are respectively displayed duringtime periods 0˜T31, T31˜T32, T32˜T33, T33˜T34. The POL signal is Logic 1when frames F31 and F33 are displayed, and becomes Logic 0 when framesF32 and F34 are displayed. When the frames F31 and F32 are displayed,the modulation signal CNTRL1 is Logic 1 and the modulation signal CNTRL2is Logic 0 according to the state of the POL signal. When the frames F33and F34 are displayed, the modulation signal CNTRL1 is changed to Logic0 and the modulation signal CNTRL2 is changed to Logic 1 according tothe state of the POL signal. Other frames can be deduced likewiseaccording to the same cycle of every four frames.

In the present embodiment, when the modulation signal CNTRL1 is Logic 1,the output voltages of the output buffers 233_1, 233_3 . . .corresponding to the modulation signal CNTRL1 are larger than theirinput voltages, that is, they are positive offset voltages. When themodulation signal CNTRL1 is Logic 0, the output voltages of the outputbuffers 233_1, 233_3 . . . corresponding to the modulation signal CNTRL1are smaller than their input voltages, that is, they are negative offsetvoltages. Likewise, when the modulation signal CNTRL2 is Logic 1, theoutput voltages of the output buffers 233_2, 233_4 . . . are larger thantheir input voltages, that is, they are positive offset voltages. Whenthe modulation signal CNTRL1 is Logic 0, the output voltages of theoutput buffers 233_2, 233_4 . . . are smaller than their input voltages,that is, they are negative offset voltages.

FIG. 3B is a voltage-to-time diagram of an ideal output waveform 301 andan actual output waveform 302 of the output buffer 233_1. When the frameF31 is displayed, the voltage of the ideal output waveform 301 is VP2,the voltage of the actual output waveform 302 is V21, and thus theoffset voltage is V21−VP2=ΔV. When the frame F32 is displayed, thevoltage of the ideal output waveform 301 is VN2, the voltage of theactual output waveform 302 is V23, and thus the offset voltage isV23−VN2=ΔV. When the frame F33 is displayed, the offset voltages isV22−VP2=−ΔV. When the frame F34 is displayed, the offset voltage isV24−VN2=−ΔV.

FIG. 3C is a voltage-to-time diagram of an ideal output waveform 303 andan actual output waveform 304 of the output buffer 233_2. When the frameF31 is displayed, the offset voltage is V34−VN3=−ΔV. When the frame F32is displayed, the offset voltage is V32−VP3=−ΔV. When the frame F33 isdisplayed, the offset voltage is V33−VN3=ΔV. When the frame F34 isdisplayed, the offset voltage is V31−VP3=ΔV.

FIG. 3D is an offset voltage distribution diagram of the frames F31˜F34according to an embodiment to the present invention. In FIG. 3D, thepositive/negative offset voltages are distributed in a column interlacedmanner. The present embodiment adopts the modulation signals CNTRL1 andCNTRL2 generated by the modulation signal generator 234 in FIG. 2C. Themodulation signal generator 234 provides the modulation signal CNTRL1 tothe output buffers 233_1, 233_3 . . . at the odd output ends andprovides the modulation signal CNTRL2 to the output buffers 233_2, 233_4. . . at the even output ends. When the frames F31 and F32 are output,the modulation signal CNTRL1 is Logic 1 and the modulation signal CNTRL2is Logic 0. When the frames F33 and F34 are output, the modulationsignal CNTRL1 is Logic 0 and the modulation signal CNTRL2 is Logic 1.The odd columns of the frames F31 and F32 are ΔV, and the even columnsare −ΔV. The effect of the offset voltages on the display quality can beeliminated by uniformly distributing the offset voltages in the space.The odd columns of the frames F33 and F34 are −ΔV, and the even columnsare ΔV. The effect of the offset voltages on the display quality canalso be eliminated by uniformly distributing the offset voltages in thespace. Other frames can be deduced likewise according to the same cycleof every four frames.

FIG. 4 is an offset voltage distribution diagram of frames F41˜F44according to another embodiment of the present invention. In FIG. 4, thepositive/negative offset voltages are distributed in a column/rowinterlaced checkerboard manner. In the present embodiment, themodulation signals CNTRL1 and CNTRL2 generated by the modulation signalgenerator 234 in FIG. 2C are changed. When the odd scan lines of theframes F41, F42 and the even scan lines of the frames F43, F44 areoutput, the modulation signal CNTRL1 at the odd output ends is Logic 1while the modulation signal CNTRL2 at the even output ends is Logic 0.When the even scan lines of the frames F41, F42 and the odd scan linesof the frames F43, F44 are output, the modulation signal CNTRL1 at theodd output ends is Logic 0 while the modulation signal CNTRL2 at theeven output ends is Logic 1. Here, the states of the modulation signalsCNTRL1 and CNTRL2 are not only changed according to the aforementionedactivating signal, but also changed according to the horizontalsynchronous signal. When the frame F41 is displayed, the first row isΔV, −ΔV, ΔV, −ΔV, ΔV, −ΔV, the second row is −ΔV, ΔV, −ΔV, ΔV, −ΔV, ΔV,the third row and the following rows can be deduced likewise. Theuniform distribution of the offset voltages ΔV and −ΔV of the frame F41can compensate the effect of the offset voltages on the display quality.The distributions of the frames F42 and F41 are the same. When the frameF43 is displayed, the first row is −ΔV, ΔV, −ΔV, ΔV, −ΔV, ΔV, the secondrow is ΔV, −ΔV, ΔV, −ΔV, ΔV, −ΔV, the third row and the following rowscan be deduced likewise. The uniform distribution of the offset voltagesΔV and −ΔV of the frame F43 can compensate the effect of the offsetvoltages on the display quality. The distributions of the frames F44 andF43 are the same. Other frames can be deduced likewise according to thesame cycle of every four frames.

FIG. 5 is an offset voltage distribution diagram of frames F51˜F54according to another embodiment of the present invention. In FIG. 5, thepositive/negative offset voltages are distributed in a row interlacedmanner. In the present embodiment, the modulation signals CNTRL1 andCNTRL2 generated by the modulation signal generator 234 in FIG. 2C arechanged. When the odd scan lines of the frames F51, F52 and the evenscan lines of the frames F53, F54 are output, the modulation signalCNTRL1 at the odd output ends and the modulation signal CNTRL2 at theeven output ends are all Logic 1. When the even scan lines of the framesF51, F52 and the odd scan lines of the frames F53, F54 are output, themodulation signal CNTRL1 at the odd output ends and the modulationsignal CNTRL2 at the even output ends are all Logic 0. The presentembodiment differs from the above embodiment in that the modulationsignals CNTRL1 and CNTRL2 are identical and the states thereof arechanged according to the horizontal synchronous signal. When the frameF51 is displayed, the odd rows are all ΔV and the even rows are all −ΔV.The uniform distribution of the offset voltages ΔV and −ΔV of the frameF51 can compensate the effect of the offset voltages on the displayquality. The distributions of the frames F52 and F51 are the same. Whenthe frame F53 is displayed, the odd rows are all −ΔV and the even rowsare all ΔV. The uniform distribution of the offset voltages ΔV and −ΔVof the frame F53 can compensate the effect of the offset voltages on thedisplay quality. The distributions of the frames F54 and F53 are thesame. Other frames can be deduced likewise according to the same cycleof every four frames.

FIG. 6 is an offset voltage distribution diagram of frames F61˜F64according to another embodiment of the present invention. Different fromthe column interlaced manner in FIG. 3D, the checkerboard manner in FIG.4 and the row interlaced manner in FIG. 5, FIG. 6 is of an asymmetricalinterlaced manner. The pixels of the frames F61˜F64 in FIG. 6 have twooffset voltages, and the numbers of the pixels having the two offsetvoltages in each of the frames F61˜F64 are almost the same. In thepresent embodiment, the modulation signals CNTRL1 and CNTRL2 generatedby the modulation signal generator 234 in FIG. 2C are changed. When aportion of the pixels of a frame is output, the modulation signalreceived by the output buffer for outputting the portion of the pixelsis Logic 1. When the other portion of the pixels of the same frame isoutput, the modulation signal received by the output buffer foroutputting the other portion of the pixels is Logic 0. In particular,when the scan lines 1, 4, 5 of the frames F61, F62 and the scan lines 2,3, 6, 7 of the frames F63, F64 are output, the modulation signal CNTRL1at the odd output ends is Logic 1 while the modulation signal CNTRL2 atthe even output ends is Logic 0. When the scan lines 2, 3, 6, 7 of theframes F61, F62 and the scan lines 1, 4, 5 of the frames F63, F64 areoutput, the modulation signal CNTRL1 at the odd output ends is Logic 0while the modulation signal CNTRL2 at the even output ends is Logic 1.In the present embodiment, the modulation signals CNTRL1 and CNTRL2 aredifferent and the states thereof are changed according to the horizontalsynchronous signal. When the frame F61 is displayed, the first, fourthand fifth rows are all ΔV, −ΔV, ΔV, −ΔV, ΔV, −ΔV, and the second, third,sixth and seventh rows are all −ΔV, ΔV, −ΔV, ΔV, −ΔV, ΔV. The uniformdistribution of the offset voltages ΔV and −ΔV of the frame F61 cancompensate the effect of the offset voltages on the display quality. Thedistributions of the frames F62 and F61 are the same. When the frame F63is displayed, the first, fourth and fifth rows are all −ΔV, ΔV, −ΔV, ΔV,−ΔV, ΔV, and the second, third, sixth and seventh rows are all ΔV, −ΔV,ΔV, −ΔV, ΔV, −ΔV. The uniform distribution of the offset voltages ΔV and−ΔV of the frame F63 can compensate the effect of the offset voltages onthe display quality. The distributions of the frames F64 and F63 are thesame. Other frames can be deduced likewise according to the same cycleof every four frames. In the present embodiment, the distributions ofthe frames 61 and 62 are the same, and the distributions of the frames63 and 64 are the same. It should be apparent to those skilled in theart that each frame can have a different distribution manner, instead ofbeing limited to the manner in the embodiment, so as to compensate theeffect of the offset voltages on the frame quality by uniformlydistributing the positive/negative offset voltages on a frame.

In the above embodiments, if the output buffer receives a modulationsignal of Logic 1, it outputs a positive offset voltage, and if theoutput buffer receives a modulation signal of Logic 0, it outputs anegative offset voltage. In other embodiments of the present invention,the corresponding relation can be opposite, i.e., if the output bufferreceives a modulation signal of Logic 0, it outputs a positive offsetvoltage, and if the output buffer receives a modulation signal of Logic1, it outputs a negative offset voltage.

The present invention not only provides a driving device in the aboveembodiments, but also provides a TFT liquid crystal display paneldriving method. The technical details of the method have been disclosedin the aforementioned embodiments, and thus will not be describedherein.

In view of the above, for different pixels of a frame in the presentinvention, the effect of the offset voltages on the display quality iseliminated by means of space modulation according to variousdistribution manners, and no capacitor is needed to store the offsetvoltages, thus saving circuit elements, preventing the frame flickeringphenomenon and improving the display quality.

Though the present invention has been disclosed above by the preferredembodiments, they are not intended to limit the present invention.Anybody skilled in the art can make some modifications and variationswithout departing from the spirit and scope of the invention. Therefore,the protecting range of the present invention falls in the appendedclaims.

What is claimed is:
 1. A liquid crystal display panel source drivingdevice, for driving a liquid crystal display panel, comprising: at leastone output buffer having chopper function; and a modulation signalgenerator, for providing at least one modulation signal to the outputbuffers; wherein, when the pixel data of a first portion of a frame isoutput, the modulation signals received by the output buffers foroutputting the pixel data of the first portion are in a first state,when the pixel data of a second portion of the frame is output, themodulation signals received by the output buffers for outputting thepixel data of the second portion are in a second state, and the numbersof the pixels in the first and the second portions are approximately thesame.
 2. The liquid crystal display panel source driving deviceaccording to claim 1, wherein the first state is either Logic 0 or Logic1, while the second state is either Logic 0 or Logic 1 and the secondstate is different from the first state.
 3. The liquid crystal displaypanel source driving device according to claim 1, wherein for each ofthe output buffers, if the modulation signal received by the outputbuffer is in the first state, the output voltage of the output buffer islarger than its input voltage, and if the modulation signal received bythe output buffer is in the second state, the output voltage of theoutput buffer is smaller than its input voltage.
 4. The liquid crystaldisplay panel source driving device according to claim 1, wherein themodulation signal generator provides a first modulation signal to theoutput buffers at the odd output ends and provides a second modulationsignal to the output buffers at the even output ends; when a first frameand a second frame are output, the first modulation signal is in thefirst state and the second modulation signal is in the second state;when a third frame and a fourth frame are output, the first modulationsignal is in the second state and the second modulation signal is in thefirst state.
 5. The liquid crystal display panel source driving deviceaccording to claim 4, wherein the states of the first modulation signaland the second modulation signal are changed according to a POL signal.6. The liquid crystal display panel source driving device according toclaim 4, wherein the states of the first modulation signal and thesecond modulation signal are changed according to a vertical synchronoussignal.
 7. The liquid crystal display panel source driving deviceaccording to claim 4, wherein the states of the first modulation signaland the second modulation signal are changed according to the firstoutput signal of a first gate driver of the liquid crystal displaypanel.
 8. The liquid crystal display panel source driving deviceaccording to claim 1, wherein the modulation signal generator provides asingle modulation signal to the output buffers; when the odd scan linesof a first frame and a second frame and the even scan lines of a thirdframe and a fourth frame are output, the modulation signal is in thefirst state; when the even scan lines of the first frame and the secondframe and the odd scan lines of the third frame and the fourth frame areoutput, the modulation signal is in the second state.
 9. The liquidcrystal display panel source driving device according to claim 8,wherein the state of the modulation signal is changed according to ahorizontal synchronous signal.
 10. The liquid crystal display panelsource driving device according to claim 1, wherein the modulationsignal generator provides a first modulation signal to the outputbuffers at the odd output ends and provides a second modulation signalto the output buffers at the even output ends; when the odd scan linesof a first frame and a second frame and the even scan lines of a thirdframe and a fourth frame are output, the first modulation signal is inthe first state and the second modulation signal is in the second state;when the even scan lines of the first frame and the second frame and theodd scan lines of the third frame and the fourth frame are output, thefirst modulation signal is in the second state and the second modulationsignal is in the first state.
 11. A thin film transistor (TFT) liquidcrystal display panel driving method, comprising: when the pixel data ofa first portion of a frame is output, providing at least one modulationsignal in a first state to at least one output buffer for outputting thepixel data of the first portion in a source driver of a TFT liquidcrystal display panel, wherein the output buffers have chopper function;and when the pixel data of a second portion of the frame is output,providing the modulation signals in a second state to the output buffersfor outputting the pixel data of the second portion; wherein the numbersof the pixels in the first and the second portions are approximately thesame.
 12. The TFT liquid crystal display panel driving method accordingto claim 11, wherein the first state is either Logic 0 or Logic 1, whilethe second state is either Logic 0 or Logic 1 and the second state isdifferent from the first state.
 13. The TFT liquid crystal display paneldriving method according to claim 11, wherein for each of the outputbuffers, if the modulation signal received by the output buffer is inthe first state, the output voltage of the output buffer is larger thanits input voltage, and if the modulation signal received by the outputbuffer is in the second state, the output voltage of the output bufferis smaller than its input voltage.
 14. The TFT liquid crystal displaypanel driving method according to claim 11, further comprising:providing a first modulation signal to the output buffers at the oddoutput ends; and providing a second modulation signal to the outputbuffers at the even output ends; wherein when a first frame and a secondframe are output, the first modulation signal is in the first state andthe second modulation signal is in the second state; when a third frameand a fourth frame are output, the first modulation signal is in thesecond state and the second modulation signal is in the first state. 15.The TFT liquid crystal display panel driving method according to claim14, wherein the states of the first modulation signal and the secondmodulation signal are changed according to a POL signal.
 16. The TFTliquid crystal display panel driving method according to claim 14,wherein the states of the first modulation signal and the secondmodulation signal are changed according to a vertical synchronoussignal.
 17. The TFT liquid crystal display panel driving methodaccording to claim 14, wherein the states of the first modulation signaland the second modulation signal are changed according to the firstoutput signal of the first gate driver of the TFT liquid crystal displaypanel.
 18. The TFT liquid crystal display panel driving method accordingto claim 11, further comprising: providing a single modulation signal tothe output buffers; wherein when the odd scan lines of a first frame anda second frame and the even scan lines of a third frame and a fourthframe are output, the modulation signal is in the first state; when theeven scan lines of the first frame and the second frame and the odd scanlines of the third frame and the fourth frame are output, the modulationsignal is in the second state.
 19. The TFT liquid crystal display paneldriving method according to claim 18, wherein the states of the firstmodulation signal and the second modulation signal are changed accordingto a horizontal synchronous signal.
 20. The TFT liquid crystal displaypanel driving method according to claim 11, further comprising:providing a first modulation signal to the output buffers at the oddoutput ends; and providing a second modulation signal to the outputbuffers at the even output ends; wherein when the odd scan lines of afirst frame and a second frame and the even scan lines of a third frameand a fourth frame are output, the first modulation signal is in thefirst state and the second modulation signal is in the second state;when the even scan lines of the first frame and the second frame and theodd scan lines of the third frame and the fourth frame are output, thefirst modulation signal is in the second state and the second modulationsignal is in the first state.
 21. A TFT liquid crystal display paneldriving device, comprising: a source driver for driving a TFT liquidcrystal display panel, comprising at least one output buffer withchopper function; and a modulation signal generator, for providing afirst modulation signal to the output buffers at the odd output ends inthe source driver and providing a second modulation signal to the outputbuffers at the even output ends in the source driver; wherein, when afirst frame and a second frame are output, the first modulation signalis in a first state and the second modulation signal is in a secondstate, and when a third frame and a fourth frame are output, the firstmodulation signal is in the second state and the second modulationsignal is in the first state.
 22. The TFT liquid crystal display paneldriving device according to claim 21, wherein the states of the firstmodulation signal and the second modulation signal are changed accordingto a POL signal.
 23. The TFT liquid crystal display panel driving deviceaccording to claim 21, wherein the states of the first modulation signaland the second modulation signal are changed according to a verticalsynchronization signal.
 24. The TFT liquid crystal display panel drivingdevice according to claim 21, wherein the states of the first modulationsignal and the second modulation signal are changed according to thefirst output signal of the first gate driver of the TFT liquid crystaldisplay panel.
 25. A TFT liquid crystal display panel driving method,comprising: providing a first modulation signal to at least one outputbuffer at the odd output ends in a source driver of a TFT liquid crystaldisplay panel; and providing a second modulation signal to at least oneoutput buffer at the even output ends in the source driver; wherein theoutput buffers have chopper function; when a first frame and a secondframe are output, the first modulation signal is in a first state andthe second modulation signal is in a second state; when a third frameand a fourth frame are output, the first modulation signal is in thesecond state and the second modulation signal is in the first state. 26.The TFT liquid crystal display panel driving method according to claim25, wherein the states of the first modulation signal and the secondmodulation signal are changed according to a POL signal.
 27. The TFTliquid crystal display panel driving method according to claim 25,wherein the states of the first modulation signal and the secondmodulation signal are changed according to a vertical synchronoussignal.
 28. The TFT liquid crystal display panel driving methodaccording to claim 25, wherein the states of the first modulation signaland the second modulation signal are changed according to the firstoutput signal of the first gate driver of the TFT liquid crystal displaypanel.
 29. A TFT liquid crystal display panel driving device,comprising: a source driver for driving a TFT liquid crystal displaypanel, comprising at least one output buffer with chopper function; anda modulation signal generator, for providing a modulation signal to theoutput buffers; wherein, when the odd scan lines of a first frame and asecond frame and the even scan lines of a third frame and a fourth frameare output, the modulation signal is in a first state; when the evenscan lines of the first frame and the second frame and the odd scanlines of the third frame and the fourth frame are output, the modulationsignal is in a second state.
 30. The TFT liquid crystal display paneldriving device according to claim 29, wherein the state of themodulation signal is changed according to a horizontal synchronoussignal.
 31. A TFT liquid crystal display panel driving method,comprising: when the odd scan lines of a first frame and a second frameand the even scan lines of a third frame and a fourth frame are output,providing a modulation signal in a first state to at least one outputbuffer in a source driver of a TFT liquid crystal display panel, whereinthe output buffers have chopper function; and when the even scan linesof the first frame and the second frame and the odd scan lines of thethird frame and the fourth frame are output, providing the modulationsignal in a second state to the output buffers.
 32. The TFT liquidcrystal display panel driving method according to claim 31, wherein thestate of the modulation signal is changed according to a horizontalsynchronous signal.
 33. A TFT liquid crystal display panel drivingdevice, comprising: a source driver for driving a TFT liquid crystaldisplay panel, comprising at least one output buffer with chopperfunction; and a modulation signal generator, for providing a firstmodulation signal to the output buffers at the odd output ends in thesource driver and providing a second modulation signal to the outputbuffers at the even output ends in the source driver; wherein, when theodd scan lines of a first frame and a second frame and the even scanlines of a third frame and a fourth frame are output, the firstmodulation signal is in a first state and the second modulation signalis in a second state; when the even scan lines of the first frame andthe second frame and the odd scan lines of the third frame and thefourth frame are output, the first modulation signal is in the secondstate and the second modulation signal is in the first state.
 34. A TFTliquid crystal display panel driving method, comprising: providing afirst modulation signal to at least one output buffer at the odd outputends in a source driver of a TFT liquid crystal display panel; andproviding a second modulation signal to at least one output buffer atthe even output ends in the source driver; wherein the output buffershave chopper function; when the odd scan lines of a first frame and asecond frame and the even scan lines of a third frame and a fourth frameare output, the first modulation signal is in a first state and thesecond modulation signal is in a second state; when the even scan linesof the first frame and the second frame and the odd scan lines of thethird frame and the fourth frame are output, the first modulation signalis in the second state and the second modulation signal is in the firststate.
 35. A liquid crystal display panel driving device, comprising: asource driver for driving a liquid crystal display panel, comprising atleast one output buffer with chopper function; and a modulation signalgenerator, for providing a first modulation signal and a secondmodulation signal to the output buffers at the output ends in the sourcedriver; wherein, two successive scan lines of the liquid crystal displaypanel is defined as a first scan-line unit, and two successive scanlines following the first scan-line unit is defined as a secondscan-line unit; when the first scan-line unit of a first frame and asecond frame and the second scan-line unit of a third frame and a fourthframe are output, the first modulation signal is in a first state andthe second modulation signal is in a second state; when the secondscan-line unit of the first frame and the second frame and the firstscan-line unit of the third frame and the fourth frame are output, thefirst modulation signal is in the second state and the second modulationsignal is in the first state.
 36. The liquid crystal display paneldriving device according to claim 35, wherein the state of themodulation signal is changed according to a horizontal synchronoussignal.